The present invention relates to a manufacturing process in semiconductor integrated circuit, and especially to a method for forming a low loss inner dielectric layer and inter-metal dielectric layer in the tungsten chemical mechanic grinding process.
With the advance in logic operation ability of integrated circuits and memory capacities, the line widths of the semiconductor elements are made smaller and smaller so that the number of layers of metal interconnecting wires must be increased continuously. The flatness between different layers becomes an important factor. With the increment of metal layers, the step heights are also increased. If the flatness process is not properly processed, the succeeding process, such lithography, etching, and other process can not be made well. The chemical mechanic grinding process is the most effective step for flatness.
Currently, chemical mechanic grinding process is widely used in the processes of shallow trench isolation, inner dielectric layer, inter-metal dielectric layer, metal lead layer, and metal plug. In the process of metal plug, the tungsten plug is the most important one. Since the melting point of tungsten is high and it has a thermal expansion coefficient correspondent to that of silicon, while the inner stress of tungsten deposited by lower pressure chemical vapor deposition (LPCVD) is not enough, further it has a preferred step covering ability. Therefore, to deposit tungsten by LPCVS to be formed with a metal plug becomes a standard manufacturing process in VLSI. Therefore, the tungsten chemical mechanic grinding process is an important process.
Tungsten chemical mechanic grinding process comprises the following steps: first, lithograph and etch an dielectric layer; secondary, sputtering titanium/titanium oxide; third, deposit tungsten metal layer by chemical gas deposition; and fourth, perform the flatness process of tungsten chemical mechanic grinding process. In above process, after depositing the dielectric layer and performing flatness by LPCVD, it is possible scratches and defects are left on the surface of the dielectric layer. To assure the tungsten metal out of the plug can be ground completely to avoid the short circuit in the succeeding metal lead, in general, over-grinding occurs, thereby reducing the thickness of the dielectric layer. Meanwhile, the dielectric layer is possible scratched due to the chemical mechanic grinding process so that in the succeeding process of forming metal leads, the metal is deposited in the scratches or the defects. This is difficult to be removed by etching so that short circuit occurs between tungsten plugs.
In abovesaid tungsten chemical mechanic grinding process, it is possible to induce the reduction of the thickness of dielectric layer or generating scratches or defects on the surface of the dielectric layer so that short circuit occurs in the succeeding process of forming metal leads. This will be described in detail by those disclosed in FIGS. 1A to 1C, which illustrated an embodiment of the inner dielectric layer. For brevity, the MOS transistor structure in the silicon substrate 10 under the inner dielectric layer is neglected. At first, as illustrated in FIG. 1A, an inner dielectric layer 12 is coated on the surface of the silicon substrate 10 and is smoothed. Next, in FIG. 1B, the inner dielectric layer 12 is lithographed for defining a plug and then is etched. Then, the deposition of the barrier layer 14 and tungsten metal layer 16 is executed. Finally, the surplus tungsten metal layer 16 and barrier layer 14 on the inner dielectric layer are ground by chemical mechanic grinding process until the inner dielectric layer 12 is exposed as illustrated in FIG. 1C so as to be formed with a plug.
Since the inner dielectric layer 12 is finally contacted directly with the grinding pad which is also used as a stop layer. To assure the above tungsten chemical mechanic grinding process can be ground completely, over-grinding is executed so that the thickness of the inner dielectric layer 12 is reduced. Since the inner dielectric layer 12 is directly in contact with the grinding pad so that scratches and defects occurs. Therefore, in the succeeding metal layer process, the tungsten plug will short circuit.
Accordingly, the object of the present invention is to provide a method for forming a low loss dielectric layer in the tungsten chemical mechanic grinding process, wherein a stop layer is used to repair the scratches or defects generated from the smoothness in the chemical mechanic grinding process. Furthermore, in the tungsten chemical mechanic grinding process, it can assure that the inner dielectric layer will not be ground so that the object of low loss is achieved.
Another object of the present invention is to provide a method for forming a low loss dielectric layer in the tungsten chemical mechanic grinding process, wherein the micro scratch generated on the surface of the dielectric layer after CMP grinding is filled completely so as to avoid the short circuit of the tungsten plug due to the scratches or defects on the dielectric layer.
Another object of the present invention is to provide a method for forming a low loss dielectric layer in the tungsten chemical mechanic grinding process, wherein after forming a dielectric layer on the semiconductor substrate and smoothing the dielectric layer as an inner dielectric layer, a stop layer of undoped silicon dioxide, organic spin on glass, or silicon oxygen nitride are coated thereon. After process of plug lithographic and etching, a barrier layer of tungsten plug and metal tungsten are deposited sequentially. Finally, the surplus tungsten metal layer on the surface of a dielectric layer is removed by chemical mechanic grinding process until the stop layer is exposed.
The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawing.